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Corso Vittorio Emanuele II, 39 - Roma 0669207671

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Ingegneria Informatica/Information and communication technologies engineering (with Helwan University) (Academic Year 2010/2011)

Computer Architecture

CFU: 5

Content language:

Course description

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Prerequisites

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Objectives

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Program

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Book

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Exercises

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Professor

Paolo Prinetto

List of lessons

• Lesson n. 1: Digital Hardware		Romeo Beccherelli
• Lesson n. 2: Binary Numbers 1/2		Romeo Beccherelli
• Lesson n. 3: Binary Numbers 2/2		Romeo Beccherelli
• Lesson n. 4: Boolean Algebra		Romeo Beccherelli
• Lesson n. 5: Logic gates and boolean functions 1/2		Romeo Beccherelli
• Lesson n. 6: Logic gates and boolean functions 2/2		Romeo Beccherelli
• Lesson n. 7: Simplification of boolean functions and Karnaugh map		Romeo Beccherelli
• Lesson n. 8: Gate level minimisation		Romeo Beccherelli
• Lesson n. 9: Combinatorial Circuits 1/3		Romeo Beccherelli
• Lesson n. 10: Combinatorial Circuits 2/3		Romeo Beccherelli
• Lesson n. 11: Combinatorial Circuits 3/3		Romeo Beccherelli
• Lesson n. 12: Synchronous sequential logic 1/3		Romeo Beccherelli
• Lesson n. 13: Synchronous sequential logic 2/3		Romeo Beccherelli
• Lesson n. 14: Synchronous sequential logic 3/3		Romeo Beccherelli
• Lesson n. 15: Synchronous Sequential Logic: Registers and Counters		Romeo Beccherelli
• Lesson n. 16: Memories		Romeo Beccherelli
• Lesson n. 17: Programmable Logic Devices		Romeo Beccherelli
• Lesson n. 18: Design at the register Transfer Logic Level RTL 1/2		Romeo Beccherelli
• Lesson n. 19: Design at the register Transfer Logic Level RTL 2/2		Romeo Beccherelli
• Lesson n. 20: Design at the register Transfer Logic Level RTL - Examples		Romeo Beccherelli
• Lesson n. 21: Basic Structure of Computers 1/2		Romeo Beccherelli
• Lesson n. 22: Basic Structure of Computers 2/2		Romeo Beccherelli
• Lesson n. 23: Instruction Set Architecture 1/5		Romeo Beccherelli
• Lesson n. 24: Instruction Set Architecture 2/5		Romeo Beccherelli
• Lesson n. 25: Instruction Set Architecture 3/5		Romeo Beccherelli
• Lesson n. 26: Instruction Set Architecture 4/5		Romeo Beccherelli
• Lesson n. 27: Instruction Set Architecture 5/5		Romeo Beccherelli
• Lesson n. 28: Basic Input/Output 1/2		Romeo Beccherelli
• Lesson n. 29: Basic Input/Output 2/2		Romeo Beccherelli
• Lesson n. 30: Software 1/2		Romeo Beccherelli
• Lesson n. 31: Software 2/2		Romeo Beccherelli
• Lesson n. 32: Basic Central Processing Unit 1/3		Romeo Beccherelli
• Lesson n. 33: Basic Central Processing Unit 2/3		Romeo Beccherelli
• Lesson n. 34: Basic Central Processing Unit 3/3		Romeo Beccherelli
• Lesson n. 35: Pipelining 1/2		Romeo Beccherelli
• Lesson n. 36: Pipelining 2/2		Romeo Beccherelli
• Lesson n. 37: Input/Output Organisation 1/2		Romeo Beccherelli
• Lesson n. 38: Input/Output Organisation 2/2		Romeo Beccherelli
• Lesson n. 39: Memory System 1/2		Romeo Beccherelli
• Lesson n. 40: Memory System 2/2		Romeo Beccherelli