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Lesson n.1:
Digital Hardware
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Lesson n.2:
Binary Numbers 1/2
- n. 2.1 -
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5
(A.Y. 2018/2019)
5
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Lesson n.3:
Binary Numbers 2/2
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Lesson n.4:
Boolean Algebra
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Lesson n.5:
Logic gates and boolean functions 1/2
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Lesson n.6:
Logic gates and boolean functions 2/2
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Lesson n.7:
Simplification of boolean functions and Karnaugh map
- n. 7.1 -
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5
(A.Y. 2018/2019)
5
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Lesson n.8:
Gate level minimisation
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Lesson n.9:
Combinatorial Circuits 1/3
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Lesson n.10:
Combinatorial Circuits 2/3
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Lesson n.11:
Combinatorial Circuits 3/3
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Lesson n.12:
Synchronous sequential logic 1/3
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Lesson n.13:
Synchronous sequential logic 2/3
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Lesson n.14:
Synchronous sequential logic 3/3
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Lesson n.15:
Synchronous Sequential Logic: Registers and Counters
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Lesson n.16:
Memories
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Lesson n.17:
Programmable Logic Devices
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Lesson n.18:
Design at the register Transfer Logic Level RTL 1/2
- n. 18.1 -
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6
(A.Y. 2018/2019)
6
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Lesson n.19:
Design at the register Transfer Logic Level RTL 2/2
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Lesson n.20:
Design at the register Transfer Logic Level RTL - Examples
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Lesson n.21:
Basic Structure of Computers 1/2
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Lesson n.22:
Basic Structure of Computers 2/2
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Lesson n.23:
Instruction Set Architecture 1/5
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Lesson n.24:
Instruction Set Architecture 2/5
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Lesson n.25:
Instruction Set Architecture 3/5
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Lesson n.26:
Instruction Set Architecture 4/5
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Lesson n.27:
Instruction Set Architecture 5/5
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Lesson n.28:
Basic Input/Output 1/2
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Lesson n.29:
Basic Input/Output 2/2
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Lesson n.30:
Software 1/2
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Lesson n.31:
Software 2/2
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Lesson n.32:
Basic Central Processing Unit 1/3
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Lesson n.33:
Basic Central Processing Unit 2/3
- n. 33.1 -
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7
(A.Y. 2018/2019)
7
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Lesson n.34:
Basic Central Processing Unit 3/3
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Lesson n.35:
Pipelining 1/2
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Lesson n.36:
Pipelining 2/2
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Lesson n.37:
Input/Output Organisation 1/2
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Lesson n.38:
Input/Output Organisation 2/2
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Lesson n.39:
Memory System 1/2
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Lesson n.40:
Memory System 2/2
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