# Ingénierie Informatique (Academic Year 2018/2019) - Ingegneria Informatica

## Multimédia

 Leçon n.1: Digital Hardware Leçon n.2: Binary Numbers 1/2 n. 2.1 - 9   (A.Y. 2018/2019) 9 Leçon n.3: Binary Numbers 2/2 Leçon n.4: Boolean Algebra Leçon n.5: Logic gates and boolean functions 1/2 Leçon n.6: Logic gates and boolean functions 2/2 Leçon n.7: Simplification of boolean functions and Karnaugh map Leçon n.8: Gate level minimisation Leçon n.9: Combinatorial Circuits 1/3 n. 9.1 - 4   (A.Y. 2018/2019) 4 Leçon n.10: Combinatorial Circuits 2/3 n. 10.1 - 5   (A.Y. 2018/2019) 5 Leçon n.11: Combinatorial Circuits 3/3 Leçon n.12: Synchronous sequential logic 1/3 Leçon n.13: Synchronous sequential logic 2/3 Leçon n.14: Synchronous sequential logic 3/3 Leçon n.15: Synchronous Sequential Logic: Registers and Counters Leçon n.16: Memories Leçon n.17: Programmable Logic Devices Leçon n.18: Design at the register Transfer Logic Level RTL 1/2 Leçon n.19: Design at the register Transfer Logic Level RTL 2/2 Leçon n.20: Design at the register Transfer Logic Level RTL - Examples Leçon n.21: Basic Structure of Computers 1/2 Leçon n.22: Basic Structure of Computers 2/2 Leçon n.23: Instruction Set Architecture 1/5 Leçon n.24: Instruction Set Architecture 2/5 Leçon n.25: Instruction Set Architecture 3/5 Leçon n.26: Instruction Set Architecture 4/5 Leçon n.27: Instruction Set Architecture 5/5 Leçon n.28: Basic Input/Output 1/2 Leçon n.29: Basic Input/Output 2/2 Leçon n.30: Software 1/2 Leçon n.31: Software 2/2 Leçon n.32: Basic Central Processing Unit 1/3 n. 32.1 - 1   (A.Y. 2018/2019) 1 Leçon n.33: Basic Central Processing Unit 2/3 Leçon n.34: Basic Central Processing Unit 3/3 Leçon n.35: Pipelining 1/2 Leçon n.36: Pipelining 2/2 Leçon n.37: Input/Output Organisation 1/2 Leçon n.38: Input/Output Organisation 2/2 Leçon n.39: Memory System 1/2 Leçon n.40: Memory System 2/2

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